1. Field of the Invention
The present invention relates to a nonvolatile random access memory that is randomly accessible, and a nonvolatile memory system.
2. Description of the Related Art
In recent years, there have been progressed development and commercialization of a ferroelectric random access memory (FeRAM), a programmable conductor random access memory (PCRAM), and a resistance random access memory (ReRAM) as nonvolatile random access memories (NVRAMs) that are capable of saving data after a power is turned off while being randomly accessible as in a case of a static random access memory (SRAM) and a dynamic random access memory (DRAM) as volatile random access memories (RAMs).
Those NVRAMs are expected as substitution of RAMs in the future, and new applications are being searched for owing to the feature of nonvolatility.
Nonvolatile memories (NVMs) typified by a flash have the feature that data retention characteristics are lowered along with an increase in the number of rewrite/deletion of memory cells. Accordingly, by adding an error correcting code (ECC) to data to be written, reliability can be improved.
The same effect is also expected with respect to the NVRAM by adding the ECC.
FIG. 1 is a diagram showing a mapping example of an NAND flash and a storage space.
FIG. 2 is a diagram showing an arrangement example of sector data and a page size of the NAND flash.
FIG. 3 is a diagram showing a processing procedure of the NAND flash at a time of update of a sector.
The NAND flash is accessed in a page PG unit as shown in FIG. 1 and accordingly is suitable for storage use in which access is made in a sector SCT unit (512 bytes).
Errors of data on a page PG can be corrected by adding an ECC as shown in FIGS. 2 and 3, with the result that the number of rewrite of data as a storage can be suppressed.
These days, a page size as a write unit is increased in the NAND flash, which causes deterioration of random access performance in a sector unit as a storage.
This is because, in order to update data of a page, it is necessary to rewrite data of all sectors SCT at least included in the page together with the ECC, as shown in FIG. 3.
In the example of FIG. 3, in a case where only a portion of a sector SCT2 of a page PG1 is rewritten, it is necessary to recalculate the ECC of the page PG1 in which the sector SCT2 is updated to new data, because the page PG1 is a write unit and is simultaneously a unit used for calculating the ECC. In addition, since the NAND flash needs deletion, it is necessary to write the updated data in a block BLKB that is different from a block BLKA, together with a newly calculated ECC.
For that reason, an apparatus that applies the NAND flash such as an SSD and a flash card to realize a storage has needed to absorb a difference among the ECC, the write unit, and the deletion unit and improve the random access performance in the sector unit.
Further, a demand for improvement of an ECC correction ability has been increased in order to suppress the number of rewrite, and a size for storing an ECC code has also been expanded.